The present invention relates to reducing the surface area of a pad limited semiconductor die layout. More specifically, the present invention relates to a method for reducing surface area of a pad limited semiconductor die layout by repositioning die pads of a common die pad group.
Typical semiconductor packages have a die that can perform complex and high speed data processing. Consequently, there is often a need for such packages to have a relatively large number of external connection pads. These connection pads are often wire bonded to input/output terminals in the form of die pads that are disposed around the periphery (edges) of the die. When low impedance or high current wire bonds are required, there are often a group of die pads wire bonded to a respective common external connection pads. As a result, the area (overall die size) of a semiconductor die may be determined by the number of die pads disposed around the periphery instead of the number of transistors forming the core or active area of the die.
When the overall die size is determined by the number of die pads, the semiconductor die is classified as a pad limited semiconductor die as opposed to core limited die which is generally limited by the number of transistors forming the core or active area of the die. Some semiconductor devices have a single row of die pads with a constant pad pitch pads disposed around the periphery of the die. The constant pad pitch is determined by the worst case packaging requirements of the semiconductor device. Furthermore, the worst case pad pitch spacing (minimum pad or bond wire pitch) is used to determine how many uniformly spaced pads fit along an edge of a semiconductor die. The problem with using a single row of bond pads that are uniformly spaced is that it can cause unnecessarily large pad limited semiconductor die sizes. In addition, even if multi-rows of bond pads are used on each side of the semiconductor die, die area reduction may not be possible because designers are required to follow design rules that specify the minimum bond wire spacing between adjacent bond wires.